1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device allowing improvement in yield.
2. Description of the Background Art
In a semiconductor integrated circuit, when diverse elements should operate in a totally independent manner without electrical interaction thereamong, it is required to provide an element isolation structure having an element isolation region.
A well-known technique of forming an element isolation region is trench isolation, on which several improvements have been suggested. According to the trench isolation technique, a trench is defined in a substrate and then filled with an insulating material. Trench isolation offers little probability of bird's beak and therefore, is recognized as one of the essential techniques of element isolation allowing shrinkage of a semiconductor integrated circuit.
A background-art method of manufacturing a semiconductor device will be described with reference to sectional views of FIGS. 24 through 28. First, a silicon oxide film 221P and a silicon nitride film 222P are stacked in this order on a silicon substrate 10P. Next, the silicon nitride film 222P, the silicon oxide film 221P and the substrate 10P are sequentially patterned using a photolithography pattern as a mask, to define a trench 11P in the substrate 10P (see FIG. 24). Following this, an inner wall of the trench 11P is thermally oxidized, to form an inner wall oxide film 223P. Thereafter a buried oxide film 21P is entirely deposited by CVD (chemical vapor deposition) (see FIG. 25).
Next, following CMP (chemical mechanical polishing) using the silicon oxide film 221P as a stopper, the buried oxide film 21P is removed in the area defined on the nitride film 222P. The buried oxide film 21P is thereafter planarized, to form a buried oxide film 20P in the trench 11P (see FIG. 26).
Thereafter, the silicon nitride film 222P is removed and the silicon oxide film 221P is removed using hydrofluoric acid. As a result, trench isolation is completed as illustrated in FIG. 27.
The next step is ion implantation for forming each well region, channel cut region and channel impurity layer for MOSFETs 201P and 202P. The channel impurity layer controls a threshold voltage of each MOSFET. Next, a gate insulating film 206, a polysilicon film 207 for forming a gate electrode, and a sidewall 208 are provided. Also provided is a source/drain diffusion layer 205 by ion implantation, thus completing a semiconductor device 1P (see FIG. 28).
As described, according to the background-art method, the buried oxide film 21P is entirely deposited by CVD, thus filling the trench 11P defined in the substrate 10P with the buried oxide film 21P.
The trench 11P will have a higher aspect ratio accompanied by increasing degree of shrinkage. Therefore, the foregoing step of filling the trench 11P generates a void in the trench 11P. After CMP and/or removal of the silicon oxide film 221P using hydrofluoric acid, such void appears on a surface of the silicon oxide film 20P, forming a minute recess. When an interconnect material for forming an upper interconnect layer is buried in such minute recess and remains therein, a short circuit may be developed in the interconnect layer. That is, generation of void results in the problem involving considerable reduction in yield of an element.